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Figure 11-1. Read Manufacturer and Device ID
CS
0
6
7
8
14 15 16
22 23 24
30 31 32
38
SCK
OPCODE
SI
9Fh
SO
HIGH-IMPEDANCE
1Fh
MANUFACTURER ID
45h
DEVICE ID
01h
DEVICE ID
00h
EXTENDED
11.2
Deep Power-down
Note: Each transition
BYTE 1
shown for SI and SO represents one byte (8 bits)
BYTE 2
DEVICE
INFORMATION
STRING LENGTH
During normal operation, the device will be placed in the standby mode to consume less power
as long as the CS pin remains deasserted and no internal operation is in progress. The Deep
Power-down command offers the ability to place the device into an even lower power consump-
tion state called the Deep Power-down mode.
When the device is in the Deep Power-down mode, all commands including the Read Status
Register command will be ignored with the exception of the Resume from Deep Power-down
command. Since all commands will be ignored, the mode can be used as an extra protection
mechanism against program and erase operations.
Entering the Deep Power-down mode is accomplished by simply asserting the CS pin, clocking
in the opcode of B9h, and then deasserting the CS pin. Any additional data clocked into the
device after the opcode will be ignored. When the CS pin is deasserted, the device will enter the
Deep Power-down mode within the maximum time of t EDPD .
The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must
be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort
the operation and return to the standby mode once the CS pin is deasserted. In addition, the
device will default to the standby mode after a power-cycle or a device reset.
The Deep Power-down command will be ignored if an internally self-timed operation such as a
program or erase cycle is in progress. The Deep Power-down command must be reissued after
the internally self-timed operation has been completed in order for the device to enter the Deep
Power-down mode.
28
AT26DF081A
3600G–DFLASH–06/09
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